1. Field of the Invention
The instant disclosure relates to a memory; in particular, to a sensing margin expanding scheme for a memory.
2. Description of Related Art
In these years, the requirement of low power, high speed and high density memory increases, due to the industry growth of mobile device, medical electrical equipment, portable storage . . . etc. Sensing margin time of the memory is the key factor which may limit the access time of the memory.
FIG. 1 shows a diagram of a sensing margin for a conventional memory. A reference voltage VREF is provided for comparing with the bit line (BL) voltage of each cell of the memory. When the bit line capacitance (CBL) is coupled to a sensing amplifier the voltage of the bit line capacitance would drop from a standard VDD as the discharge-time passes. For example, the reference voltage VREF would be defined as larger than the bit line voltage as the discharge-time passes when the bit line store ‘1’, and the bit line voltage would be lower than the reference voltage VREF as the discharge-time passes when the bit line store ‘0’. A sensing margin time of the bit line voltage is needed for obtaining a distinguishable voltage difference (compared with the offset of the sense amplifier) inputted to the sense amplifier. With low supply voltage, a sense amplifier needs more read margin against PVT variation. Conventional read scheme suffers from slow margin developing and thus has longer access time.